library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity qianga is
port(esa,esb,esc,esd:in bit;
rst:in std_logic;
lta,ltb,ltc,ltdut bit);
end qianga;
architecture Behavioral of qianga is
signal data1:bit_vector(3 downto 0);
begin
process(rst,data1,esa,esb,esc,esd)
begin
if rst='0'
then lta<='0';ltb<='0';ltc<='0';ltd<='0';
else
data1(3)<=esa;
data1(2)<=esb;
data1(1)<=esc;
data1(0)<=esd;
end if;
case data1 is
when "0001"=>lta<='1';ltb<='0';ltc<='0';ltd<='0';
when "0010"=>lta<='0';ltb<='1';ltc<='0';ltd<='0';
when "0100"=>lta<='0';ltb<='0';ltc<='1';ltd<='0';
when "1000"=>lta<='0';ltb<='0';ltc<='0';ltd<='1';
when others=>lta<='0';ltb<='0';ltc<='0';ltd<='0';
end case;
end process;
end Behavioral;
有个电子技术实验让做个抢答器，昨天看了一天，刚刚编了一个，语法没错了，不知道能不能实现呢，4位抢答，各位帮忙看看哈，我也是学通信的啊，不知道为啥有这个实验
ut bit);
