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注册:2005-12-17
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发表于 2013-4-1 15:20:35 |只看该作者 |正序浏览
  • Array of 64 purpose-built programmable processing elements
  • Standard-based 100 GbE, 40 GbE, 10 GbE, and 1 GbE support
  • Direct connect to optical modules
  • Large-scale hardware acceleration of key functions:
    - Packet parsing and classification of packet headers
    - ACL rules on-chip with external expansion via TCAM
    - L2/L3/L4 table scalability with low-cost DDR3 SDRAM
    - Counters/statistics support in deep on-chip memory
    - RFC-2697/2698/4115- and MEF-compliant policers on-chip
  • Layer 2 bridging, IEEE 802.3™, IEEE 802.1q, IEEE 802.1ad PB, IEEE 802.1ah PBB

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