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标题: Xlinx RRH  [查看完整版帖子] [打印本页]

时间:  2020-9-23 20:16
作者: Vortex     标题: Xlinx RRH

2 Antenna 2x20MHz (40MHz) LTE Radio Solution



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Employing the dual ARM® Cortex™-A9 MPCore processors in Zynq®-7000 devices and the highly scalable radio SmartCORE™s and Connectivity IP enables extremely low power, low cost and small footprint solutions ideal for radio applications. Whether it be a narrow band single antenna small cell, or wide band multi-antenna macrocell, the Zynq SoC family of devices provides the most flexible, most integrated and programmable solution available today, providing risk mitigation with late feature changes, and even supporting feature enhancements post deployment.







Solution Summary and Benefits



  • 3 chips into 1: Combining radio control processing (O&M), signal processing for DUC/DDC, CFR and DPD, with connectivity IP for JESD204B and CPRI
  • Scalable to support multiple antennas and carrier configurations
  • ARM Cortex A9 + NEON for high speed digital signal processing in software
  • CPRI support for up to 9.8Gbps line rates with auto-negotiation
  • Optional digital VCXO and jitter cleanup PLL implementation
  • Lowest overall power and cost, with maximum integration and solution flexibility












SmartCORE IP Solutions



  • DUC/DDC Compiler
  • PC-CFR
  • DPD










LogiCORE IP Solutions



  • FIR Compiler
  • DDS Compiler
  • JESD204B
  • CPRI
  • OBSAI
  • Ethernet

Reference Designs

  • WCDMA/CDMA2000 DUC/DDC Reference Design
  • WiMAX DUC/DDC Reference Design
  • CPRI Multi-hop Reference Design










Hardware Platforms



Boards and Kits

  • Tektelic High Performance Radio Card
  • Avnet DSP Kit












Programmable Logic Functions



  • 491MHz capable logic fabric (Kintex®-7/Virtex®-7) for efficient low power implementation of filter structures found in DUC/DDC, CFR and DPD processing
  • CPRI/ OBSAI framer/de-framer and application layer with high-speed SerDes
  • JESD204B framer/de-framer and application layer with high-speed SerDes
  • High-speed LVDS interfacing for legacy DAC/ADC technology











Processor Sub-System Functions



  • Radio control, calibration, alarms and message termination
  • Digital pre-distortion correction algorithms leveraging ARM + NEON and optional fabric-based hardware accelerators











8x8 100 MHz TD-LTE Remote Radio Unit




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Key UltraScale+™ Portfolio Benefits



  • Quad-core ARM® Cortex™-A53 for implementation O&M processing and DPD
  • Dual-core ARM Cortex-R5 real-time coprocessor for wireless protocol software
  • 491 MHz pushbutton timing closure in low-power speed grade and up to 825 MHz in normal speed grade
  • Support for 12.5G transceivers in low-power speed grade (CPRI, JESD204B)
  • Up to 128 power-optimized transceivers at 33 Gb/s (25G Ethernet, 16/25G CPRI, 25G JESD204B/C, 28G backplane)
  • W-Mux DSP48 for efficient complex filter implementation
  • UltraRAM for fiber length delay compensation
  • Power management unit (PMU) to dynamically optimize power
  • UltraScale® architecture, 16FinFET+, and PMU combine to deliver performance, and low-power speed grades to reduce thermal challenges
  • Dedicated configuration security unit (CSU) for IP, waveform, and tamper protection







时间:  2020-9-23 23:27
作者: 没事来看看

能用硬件实现的,总比软件来的要靠谱,包括性能 时延 功耗 体积,甚至是成本




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